This invention relates to computer systems and more particularly, to the pre-fetching of data from a computer system having error checking and correcting features.
In order to reduce memory overhead in memory systems with error checking and correction, a wide memory word is desirable. For a 256K byte system with double bit error detection and single bit error correction, implemented with 64K bit dynamic RAM, a total of 44 dynamic RAM devices are required if a 16 bit wide word is used, while only 39 dynamic RAM devices are required if a 32 bit word is used. In addition to requiring extra memory devices, error correcting memories are inherently slower than comparable width non-error correcting memories constructed from equivalent devices because of the checking time required for each read cycle. Further, if the memory word is wider than the processor data path, as is desirable for reducing memory chip overhead, then all memory write cycles are required to read-modify-write (R-M-W) cycles. R-M-W cycles take approximately twice the time to complete as simple write cycles on non-ECC memories and have an additional adverse impact on the performance of an ECC Memory System.
The present invention directs itself to overcoming the performance degradation due to the 32 bit wide memory word. Performance for the 32 bit wide memory can be made greater than that for a 16 bit wide memory by adding pre-fetch logic to the memory control. Large scale integrated circuit (LSI) error correction devices (ECC's) can be cascaded for use in 32 bit wide memory systems. These error correcting devices have output data latches that store corrected data during memory read cycles, and these latches are individually addressable on a byte basis. The present invention takes advantage of the fact that four bytes, or two words, are stored on each memory read. Additional circuitry can be added to detect when the currently-accessed byte or word is in the same four byte address space as the last read byte or word. When this condition is detected, the memory is not cycled since the data is already present at the output latches of the ECC devices. The addressed byte, or word, is enabled onto the data bus from the appropriate ECC output latches. The access time of the memory, as seen by the processor in this instance, is much shorter than that required by the fastest 16 bit MOS processors currently available.
Of interest is U.S. Pat. No. 4,156,905 entitled Method and Apparatus for Improving Access Speed in a Random Access Memory by C. J. Fassbender. In that patent, an address having a first and second portion is utilized to address a group of words from memory, using the first address portion. The group of words are stored in output registers and the second address portion is utilized to select particular words contained in the output registers. A number of second address portions may be used in any processor cycle. When a subsequent group of words is to be accessed, a second first address portion is loaded into a pre-fetch register and the previously loaded first address portion is compared with the second first address portion to determine if they are the same. If they are, then the need for loading a group of words into the output registers is eliminated. If they are not the same, a miscomparison signal is generated to clock a new group of words into the output registers. The method and apparatus of the above-referenced patent performs its function adequately, but does require that the address contain two separate portions and a modification in the method of addressing has to be implemented.
In the present invention, the basic system operation remains unchanged from the standard mode, the main difference being the utilization of the probability that the next-to-be-accessed word has previously been accessed and appears somewhere within the hardware of the computer system.